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Daniel Nenni

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Open-Silicon SiFive and Customizable Configurable IP Subsystems

Posted by Daniel Nenni on Feb 13, 2019 6:39:39 AM

Published on 02-01-2019
Published by SemiWiki

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RISC-V End to End Solutions for HPC and Networking

Posted by Daniel Nenni on Dec 28, 2018 8:19:58 AM

Published by SemiWiki on 11-30-2018

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Custom SoC Platform Solutions for AI Applications at the TSMC OIP

Posted by Daniel Nenni on Sep 30, 2018 2:53:06 AM

Published by SemiWiki
Published on 09-27-2018

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Deep learning fueling the AI revolution with Interlaken IP Subsystem

Posted by Daniel Nenni on Jul 31, 2018 12:20:33 PM

Published by SemiWiki
Published on 07-30-2018

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TSMC OIP DAC Theater Schedule 2018

Posted by Daniel Nenni on Jun 23, 2018 3:41:00 AM

Published by SemiWiki
Published on 06-20-2018

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Webinar: Custom SoCs for Narrowband IoT

Posted by Daniel Nenni on May 31, 2018 1:12:50 AM

Published by SemiWiki
Published on 05-30-2018

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FlexE at SoC IP Days with Open-Silicon

Posted by Daniel Nenni on Apr 2, 2018 7:18:31 AM

Published by
Published on 03-30-2018

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Herb Reiter on the Challenges of 2.5D ASIC SiPs

Posted by Daniel Nenni on Mar 1, 2018 1:34:55 AM

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Published on 02-23-2018

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Open-Silicon Year in Review 2017

Posted by Daniel Nenni on Mar 1, 2018 1:29:15 AM

Published by
Published on 01-31-2018

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Free IoT SOC Books at REUSE 2017

Posted by Daniel Nenni on Dec 13, 2017 8:15:10 AM

Published by SemiWiki
Published on 12-08-2017

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Free eBook: Custom SoCs for IoT: Simplified

Posted by Daniel Nenni on Nov 22, 2017 4:51:11 AM

Published by SemiWiki
Published on 10-16-2017

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High Bandwidth Memory ASIC SiPs for Advanced Products!

Posted by Daniel Nenni on Oct 5, 2017 4:56:09 AM

Published by
Published on 08-30-2017

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Custom SoCs for IoT Revolution!

Posted by Daniel Nenni on Jul 31, 2017 5:01:21 AM

Published by
Published on 07-21-2017
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Open-Silicon Update: 125M ASICs shipped!

Posted by Daniel Nenni on Feb 6, 2017 4:04:48 AM

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Webinar: Improve Security For IoT Edge Devices With Custom SoCs

Posted by Daniel Nenni on Dec 1, 2016 2:12:46 AM

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CEO Interview: Taher Madraswala of Open-Silicon

Posted by Daniel Nenni on Nov 2, 2016 4:42:53 AM publication, October 31, 2016

Taher Madraswala started his career at Intel designing microprocessors and later overseeing ASIC development before joining Open-Silicon at its inception. During his 25 year semiconductor career Taher has experienced more than 300 tapeouts across a wide variety of applications.

Today Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has shipped over 120 million ASICs to date.

How do you view the current state of the ASIC market?
We believe we are at a real crossroad of choices that the industry will make on custom silicon. While Networking, Telecom, Storage and Computing (NTSC) applications are pushing the performance envelope with leading edge process technologies, mixed signal/ IoT applications are leveraging the mature process technologies that are optimized for low power applications. Even though many platform designers will want to create a differentiation with custom hardware, the rising cost of masks and wafers may make them rethink. However, ASIC enabled product differentiation provides a competitive advantage for many applications. Those who run the race of performance, power and product differentiation to distinguish their solutions will continue investing in ASICs.

What do you see as barriers to growth and innovation?

Lack of appetite to fund new architectures in silicon and a shrinking ecosystem of IP providers. To overcome this barrier, Open-Silicon has joined forces with Silicon Catalyst, which is an incubator for semiconductor solution startups to enable them to increase silicon innovation opportunities and pursue big ideas at a much lower cost through strategic partners. Reducing upfront costs enables startups to become higher value investments. Follow-on funding then leads to true innovation and value creation.

What kinds of design/technology innovations do you think are the biggest game changers, and why?
There are two. One is ASIC development platforms. These platforms can speed custom design while retaining the ability to differentiate. Creating ASIC platforms requires thinking like a system company, or even like a startup, and requires the consideration of end use cases.

The other is packaging technology, specifically system in a package (SiP) and 2.5D. These will have a large impact on the future of our industry by creating a new wave of system integration techniques that will exploit the benefits of the footprint compression that these packaging technologies provide.

How is Open-Silicon helping to bring these innovations to fruition?
We are investing in ASIC development platforms for emerging applications. Our Specification-to-Chip IoT ASIC Platform is a perfect example. Open-Silicon’s IoT platform includes pre-designed Register-Transfer Level (RTL) field-proven components along with a support ecosystem of software and services for a variety of protocols, operating systems and analytics. The design is scalable and allows for variations in hardware/software partitioning, as well as the integration of custom IP. With the hardware blocks already designed and the associated software already developed, the project can begin at a point that is months ahead of a full custom design.

We are also aggressively investing in solving the die-to-die and processor-to-memory links with internally developed IP, such as our High Bandwidth Memory (HBM) total solution and interposer technology development to support the SiP and 2.5D technologies.

Open-Silicon provides full turnkey ASIC solutions translating customer ideas into real silicon. Why is this significant?

The industry is transitioning very quickly from innovating at the hardware level to innovating at the application level. By providing expertise that can translate ideas into real silicon, we encourage and help innovators spend more of their time in listening to their customers rather than building and managing infrastructure to implement their ideas. From self-driving cars to virtual reality, the inventors and idea managers should invest their time into defining ground-breaking concepts. We want to help revive innovation by allowing dreamers to think and envision, rather than just manage.

What advancements in technologies, like 2.5D and HBM, is Open-Silicon working on that you would like to share with SemiWiki subscribers?
Open-Silicon made an early investment in 2.5D, which has allowed us to offer an ASIC package with integrated 3D memory stacks using silicon interposer 2.5D technology. The result is higher performance, lower power and a smaller form factor system — a three-way win. 2.5D and 3D stacking creates ways to mix and match chip components, meaning products can be divided into multiple dies. Some functions can be at a less expensive process node, or mixed with other functions that require a high frequency and/or low power.

Another significant advancement is Open Silicon’s HBM IP subsystem, which enables 1024-bit wide memory paths to ASICs using a 2.5D SiP solution. ASIC applications in networking, deep learning, virtual reality, gaming, cloud computing and data centers can improve their access to memory by applying this HBM SiP approach along with the necessary IP and JEDEC-compliant HBM memory chips, which come in stacked-die 3D versions.

What advice would you give to students or to those just entering the field of chip design engineering?
This is one of the most exciting times to be innovating with semiconductors. Never has there been more focus on the ability to interface machines with human users. Mega-trend opportunities in IoT, biotech, wearables, energy, autonomous vehicles and mobile will all have new semiconductor innovation at their core. You are joining a workforce that will continue to profoundly change the lives of humans, and that is both exciting and extremely rewarding. 

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The Role of IP Selection and Integration in First-Time Silicon Success

Posted by Daniel Nenni on Sep 21, 2016 9:07:46 AM Publication

As IP expert Eric Esteve has written, Semiconductor IP has consistently outgrown the other design enablement segments and will continue to do so. This has been my personal experience as well during my EDA and IP career so we should all know how important Semiconductor IP is. We certainly know how valuable it is with ARM valued at $32B!

Also read: Design IP Growth Is Fueling 94% of EDA Expansion

Since the beginning of SemiWiki, Semiconductor IP has driven the most traffic. As of today there have been 640 IP blogs published on SemiWiki that have been viewed a total of 2,739,472 times, absolutely! Some of the top IP search terms we have seen are: IP Verification, IP Integration, IP Validation, Low Power IP and of course IP Selection, which brings us to the latest Open Silicon Webinar:

The Role of IP Selection and Integration in the Achievement of First-Time Silicon Success

This Open-Silicon webinar will address key considerations when selecting and integrating IP into ASIC/SoC designs. No longer can the procurement and integration of third-party IP be done in isolation as just an IP block. System issues associated with choosing the right hardware, appropriate firmware and optimum embedded software in which the ASIC/SoC will fit, is now the biggest driver for third-party IP procurement. As a result, navigating the many challenges associated with blending diverse IP from multiple vendors, increasing software complexity, design challenges in process manufacturing, hardware implementation and emulation, trade-offs in system architecture, and maintaining compliance with ever-evolving standards, is the key to successful integration and first-pass silicon.

Those joining the webinar will learn what third-party IP vendors and turnkey ASIC solutions providers are doing from a system perspective down to the transistor level, to not only mitigate these challenges and facilitate seamless integration, but reduce cost and incorporate greater flexibility and functionality while maintaining the system perspective using pre-verified and customized IP blocks. The panelists will delve deep into the architectural deliverables, trade-offs on IP selection, and quality benchmarks that enable the best performance of an ASIC/SoC for any specified application or operating condition. This includes compatibility assurances across all of the IPs front/back-end views and deliverables within any specific tool flow, as well as the foundry processes. Other topics to be discussed include system level checklists, integration checklists, integration reviews, tape-out reviews, certifications, evaluation boards and more.

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The ASIC Business Model is Critical for the DIY and Maker Movements!

Posted by Daniel Nenni on May 23, 2016 5:26:15 AM

SemiWiki publication

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