Silicon Blog

Eric Esteve

Recent Posts

Multi-Channel Multi Rate FEC Engine Webinar with Open-Silicon

Posted by Eric Esteve on Nov 30, 2017 8:24:07 AM

Published by SemiWiki
Published on 11-29-2017

Read More

Webinar: Achieving Very High Bandwidth Chip-to-Chip Communication with the Interlaken Interface Protocol

Posted by Eric Esteve on Jun 8, 2017 5:03:36 AM

Published by on 06-05-2017 10:00 AM

Open Silicon will hold this webinar on June 13th at 8 am PDT (or 5 pm CE) to describe their Interlaken IP core, and how to achieve very high bandwidth C2C communication in various networking applications. To be more specific, the Interlaken protocol can be used to support Packet Processing/NPU, Traffic Management, Switch Fabric, Switch Fabric Interface, Framer/Mapper, TCAMs or Serial Memory (INLK-LA). Open Silicon is marketing the Interlaken IP core for ASIC, but the networking industry also loves FPGA technology, offering fast Time-to-Market (TTM) and, even more important, well-known advantage of flexibility, allowing to support protocol evolution in the field. The Interlaken protocol also supports FPGA implementation.

There are significant demands for performance and bandwidth in high-speed communications, and pressure to step up the pace on technological advancements. The panelists will outline the challenges that designers of advanced communication applications encounter with things like controller specification, latency, various SerDes architectures and implementation. They will outline use cases and discuss the key technical advantages that the Interlaken IP core offers, such as 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC), as well is its multiple user-data interface options. They will also discuss the architectural advantages of the core, such as its flexibility, configurability and scalability.

I am very honored as I have been asked by Open Silicon to be the moderator of this webinar. But you must deserve such honor and to some homework to be well prepared, and I will share with Semiwiki readers some bits of information about Interlaken, so you (the reader) will also be well prepared!

Meeting these requirements from the Interlaken Alliance will ensure interoperability for different implementations (don’t forget that Interlaken is a chip-to-chip communication protocol, so interoperability is key):

Supports multiple parallel lanes for data transfer at physical level
User interface packet based. With each packet consisting of multiple bursts
Simple control word to delineate packet and bursts
Protocol independence from the number of SerDes lanes and SerDes rates
Ability to communicate per-channel backpressure
Performance scales with the number of lanes

I think that most of the points in this list are clear enough, with probably the notable exception of per-channel backpressure. If you are (like me) not aware about this concept, you will have to dig to understand the meaning and implication of per-channel backpressure. Don’t worry, I did it, and found this definition:
In queueing theory, a discipline within the mathematical theory of probability, the backpressure routing algorithm is a method for directing traffic around a queueing network that achieves maximum network throughput which is established using concepts of Lyapunov drift. Backpressure routing considers the situation where each job can visit multiple service nodes in the network. It is an extension of max-weight scheduling where rather each job visits only a single service node.

To make it simple:

Read More

1.2 Terabit/s C2C Interface? Only with Interlaken!

Posted by Eric Esteve on May 3, 2017 6:14:33 AM

Published by,  on 04-24-2017

If you are familiar with high bandwidth networking applications, you probably know this chip-to-chip (C2C) interface protocol. Interlaken architecture, fully flexible, configurable and scalable, is also an elegant answer to the need for very high bandwidth C2C communication. Interlaken is elegant because the protocol defines the controller specification and can interface with various SerDes architectures, up to 56 Gbps SerDes rates with Forward Error Correction (FEC).

The Interlaken protocol has clearly been defined to provide the lowest latency when interfacing two chips at very high speed. The definition is simple, allowing the best possible efficiency. If you compare Interlaken specification with PCI Express or Ethernet for example, it’s much, much simpler, making the protocol easy to implement albeit extremely powerful to connect devices together.

Read More

Knowledge Powerhouse

Open-Silicon blog provides knowledge on latest technology and industry developments in ASIC space. It helps engineers and analysts with solutions they might be looking for. Your comments can help clarify the doubts, add knowledge and lay foundation for future innovations.

Recent Posts

Subscribe to Email Updates