Silicon Blog

Careful IP Integration Key to First-Pass Silicon

Posted by Vamshi Krishna on May 3, 2016 6:54:45 AM

EETimes publication

Follow these four aspects of IP integration to allow first-pass ASIC silicon when using IP from multiple vendors.

Most ASIC companies today rely on third-party IP in building a custom ASIC/SoC. While ensuring convenience in terms of flexibility, schedule, and cost effectiveness, however, this approach can also present challenges. IP companies, although they adhere to common Industry standards, typically follow different IP development processes, apply different quality benchmarks, and provide different deliverables. The fact that each IP block is unique with respect to its function creates even more differentiation. All this variability makes it difficult to assemble an ASIC using IP from multiple sources and achieve first-pass silicon.

It is possible to achieve first-pass silicon, however, by following a careful integration process. Here are four aspects that ASIC design companies have to consider when using IP blocks from different vendors.

IP Delivery Check

The IP team at a design house must ensure that every IP delivery is complete, accurate, and adheres to the project flows, methodology, and schedule. But the parameters for a successful IP delivery depend on the product application requirements. In addition to maintaining a checklist for the receipt of all an IP block's standard front-end and back-end views, for instance, it may be important to the project that there be non-standard views of the IP included in the checklist. For example, some designs may need a spice netlist for re-characterization of the IP at some non-standard temperatures and voltages. Some projects may also require IBIS models for system design.

The IP team must also ensure that all collateral received as a part of delivery complies with the other IPs in the design, as well as the tool flows the team uses for integration. This compliance is particularly important when integrating IP from various providers. Other elements to consider include parameters such as process node, metal stack, oxide voltages, and Vt for devices. In some cases, input constraints needed by EDA tools could also be different, especially if the IP vendor develops and delivers IP that uses tools from one EDA vendor, and the design house uses a different set of tools from another EDA vendor for integration of the IP (e.g. Synopsys vs Cadence). The use of different tools can result in input constraint files that may require modifications.

IP Quality Check

Upon receipt of the IP deliverables, the IP team must ensure all deliverables are consistent with respect to versioning, compatibility across IP views, and documentation. Even if the IP comes from a reputed vendor or is silicon proven, it is strongly recommended to re-run DRC, LVS, ERC, and antenna checks along with pin-to-pin compatibility across Verilog, LIB, LEF, and GDS to ensure there are no design or consistency issues. RTL simulations must be run to ensure functional accuracy of the IP. However, there is no defined methodology for verifying functional accuracy in the back-end views. The best way to mitigate this risk is to consider a silicon-proven IP for the design.


Integration Checklists

Preparing and adhering to an integration checklist for every IP is an important step in ensuring correct IP integration into an ASIC/SoC. An integration checklist can be prepared by leveraging various resources, including an IP Integration guide, an IP data book, previous design experiences, IP knowhow, and best practices of integration at various stages, to name a few. Once an integration checklist is prepared, it has to be meticulously followed and converged on at every milestone of the project.

The integration checklist should consist of all aspects of IP integration, such as place and route, timing analysis, power analysis, design for testability, and electrical and interface considerations, like IO pad ring design, ESD and signal integrity.

Integration and Tape-Out Reviews

At Open-Silicon we follow a design process that consists of 5 stages – Explore, Analyze, Implement, Converge, and Tape-Out. At the end of each stage, an integration review is conducted with the IP Integration teams and the customer. These reviews keep the IP integration requirements as well as customer expectations aligned with each other at every stage of the project.

An integration review with IP vendors, IP integration teams, and the customer is especially recommended during the Converge phase of project to ensure that all stakeholders are in agreement. Reputed IP vendors always choose to help the design house by reviewing the IP floorplan and implementation details. This support provides the customer an additional layer of confidence before project tape out. A mock tape out also helps streamline foundry manufacturing flows and requirements and avoid any last minute surprises during actual tape-out.


 Any issues found during the quality check or integration review process will have ample time for the IP vendor to fix any issues, which would otherwise be known only post tape-out. The cost of fixing an issue post tape out is significantly higher than getting it fixed before tape out.

By thoroughly adhering to these four steps for careful IP integration, ASIC/SoC design houses can blend diverse IP from multiple vendors, achieving first-pass silicon while keeping the NRE low and the schedule intact.

Vamshi Krishna is Sr. FAE and IP Solutions Manager with Open-Silicon, and is responsible for managing third party IP function which involves selection, procurement, quality check and Integration of various Enterprise and Consumer application IPs. Prior to joining Open-Silicon, Vamshi was Hard IP Applications Engineer at Intel and Product Applications Engineer at MosChip Semiconductor, and was responsible for IP/Product Quality check, delivery, and support. Vamshi holds a Bachelor of Technology Degree in the stream of Electronics and Communications Engineering from Kakatiya University, India.


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