Today's characterization tools offer a very good solution for extracting the best performance out of an ASIC/SoC for any specified PVT operating conditions.
A typical corner (TT) is no longer typical for most applications in today's world. For that matter, standard PVT Corners (FF/TT/SS), generally, do not represent the exact environmental conditions in which an ASIC/SoC will be functioning. This means the voltage may not be a nominal Vdd in a typical case or Vdd±10% in an extreme case; and the temperature may not be 25C in a typical case or 125C/-40C in extreme cases. Also, in today's market, every µW of power saved, and nS of delay avoided, makes a significant difference in a product's performance and cost. Therefore, it is important to know how a system behaves under real-time PVT conditions. One needs to characterize foundation IPs at these special (custom) corners to avoid overdesign and achieve optimal product for best power and performance.
When estimating the power and timing numbers of an IP at a custom corner (e.g., @95C and Vdd+3%), it is not easy to derive values from regular SS, TT, and FF characteristics as these may not support linear extrapolations. Even small errors in calculation can be very risky. One approach is to use characterization tools (e.g., Silicon Smart from Synopsys) that can easily characterize foundation IPs to estimate power and performance of an SoC at any custom corner with substantial accuracy using reference ".lib" files.
In order to generate an accurate custom corner ".lib" file, one must ensure that a reference ".lib" file, which is already provided by an IP vendor, can be generated using the setup. The better co-relation achieved ensures more accurate ".lib" generation for the custom corner. Various options and settings available in the tool enable proper alignment of setup to adhere to the processes followed by different vendors to generate highly accurate ".lib" files. The tool also provides the flexibility to choose between different simulator environments available in the market (e.g., HSpice, Spectre).
A case study illustrating the success of custom corner characterization performed on 28nm foundation IP is one where Open-Silicon used Synopsys' SiliconSmart characterization tool to generate highly accurate results.
To begin, an available standard corner .lib file was generated using a characterization tool to ensure proper correlation. In this case, we re-characterized the scan flip-flop's typical corner .lib provided by the vendor (nominal voltage and 25C temperature). The results show that the correlation was very accurate. In the graphs below, one can see that the blue reference curves are almost entirely overlapped by the orange test curves.
When such correlations are obtained, one can confidently rely on the setup to generate any customer corner .lib files as needed by the design.
The historical process of using extrapolation to measure a standard cell library's performance to changing voltage or temperature is starting to fade away. The complexity involved, the effort required, and the accuracy of constraints required means that a traditional extrapolation process is simply un-affordable. Characterization tools, by comparison, can easily execute a handful of commands, generate highly accurate (close to 100%) result,s and deliver more efficiency. The end result is that today's characterization tools offer a very good solution for extracting the best performance out of an ASIC/SoC for any specified PVT operating conditions.
- Heterogeneous System Architecture: A New Computing Platform Infrastructure
- FPGA Debug in the Modern World
- MCU Guy, Meet FPGA; FPGA, Meet MCU Guy
- Madcap Ultrasound Engineers Send FPGA to 103,000 Feet
- Proceedings of the IEEE: Design Automation of Electronic Systems
- Programmable ASSP (pASSP) I/F Bridge for Mobile Image Sensors & Displays
- FPGA-Based Real-Time Spectrum Analyzer Sets New Record
Join over 2,000 technical professionals and embedded systems hardware, software, and firmware developers at ESC MinneapolisSeptember 21-22, 2016, and learn about the latest techniques and tips for reducing time, cost, and complexity in the development process.
Make sure to follow updates about ESC Minneapolis's talks, programs, and announcements via the Destination ESC blog on Embedded.com and social media accounts Twitter, Facebook, LinkedIn, and Google+.
The Embedded Systems Conference and EETimes.com are owned by UBM Canon.