Published by SemiWiki
Published on 09-27-2018
The TSMC OIP event is next week and again it is packed with a wide range of technical presentations from TSMC, top semiconductor, EDA, and IP companies, plus long time TSMC partner and ASIC provider Open-Silicon. You can see the full agenda HERE.
AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher memory bandwidth. ASIC platforms enable AI applications through training in deep learning and high speed inter-node connectivity, by deploying high speed SerDes, a deep neural network DSP engine, and a high speed high bandwidth memory interface with High Bandwidth Memory (HBM) within a 2.5D system-in-package (SiP). Open-Silicon’s implementation of a silicon-proven ASIC platform with TSMC’s FinFET and CoWoS® technologies is centrally located within this ecosystem.
Open-Silicon’s first HBM2 IP subsystem in 16FF+ is silicon-proven at 2Gbps data rate, achieving bandwidths up to 256GBps, and being deployed in many ASICs. The data-hungry, multicore processing units needed for machine learning require even greater memory bandwidth to feed the processing cores with data. Keeping pace with the ecosystem, Open-Silicon’s next generation HBM2 IP subsystem is ahead of the curve with 2.4Gbps in 16FFC, achieving bandwidths up to >300GBps.
This 7nm ASIC platform is based on a PPA-optimized HBM2 IP subsystem supporting 3.2Gbps and beyond data rates, achieving bandwidths up to >400GBps. It supports JEDEC HBM2.x and includes a combo PHY that will support both JEDEC standard HBM2 and non-JEDEC standard low latency HBM. High speed SerDes IP subsystems (112G and 56G SerDes) enable extremely high port density for switching and routing applications, and high bandwidth inter-node connections in deep learning and networking applications. The DSP subsystem is responsible for detecting and classifying camera images in real time. Video frames or images are captured in real time and stored in HBM, then processed and classified by the DSP subsystem using the pre-trained DNN network.
Implementation challenges for AI ASICs include design methodologies for advanced FinFET nodes, physical design of large ASIC >300 mm2 running at GHz speed, power and timing closure, system level power and thermal and timing signoff. Open-Silicon has overcome these challenges with advanced implementation strategies that enable Advanced On-Chip Variations (AOCV) flow for physical design and timing closure, correlation between implementation and signoff that results in faster design convergence, an advance node power plan and validation techniques, and system level signal and power integrity signoff for a complete 2.5D SiP. Additionally, various in-house development tools help debug and analyse the design data through physical design phases, thus speeding convergence of complex designs.
Open-Silicon’s DFT methodology enables the test and debug challenges in large ASIC designs by incorporating methods such as core wrappers, hierarchical BIST/scan, compression, memory repair, power aware ATPG and enablement of wafer probing to ensure quality KGD before 2.5D assembly, interconnect test between ASIC and HBM, and incorporating design practices recommended by TSMC CoWoS® to improve 2.5D SiP manufacturing and yield.
Open-Silicon’s ASIC design and test methodology, low area high performance HBM2 IP subsystem, and its experience in high speed SerDes integration and DSP subsystem implementation, offer best-in-class custom silicon solutions for next generation AI and high performance networking applications.
Who: Bhupesh Dasila, Engineering Manager – Silicon Engineering group, Open-Silicon
What: Custom SoC Platform with IP Subsystems Optimized for FinFET Technologies
Enabling AI Applications
When: Wednesday, October 3 2018, 1:00 pm
Where: Open-Silicon Booth, #907
The TSMC Open Innovation Platform® (OIP) Ecosystem Forum is a one-of-a-kind event that brings together the semiconductor design chain community and approximately 1,000 director-level and above TSMC customer executives. The OIP Forum features a day-long, three-track technical conference along with an Ecosystem Pavilion that hosts up to 80 member companies.