Using ring oscillators to validate design signoff methodology and silicon process.
The sensitivity of digital circuits to process variations is continuously increasing with scaling in MOSFET devices. The effect of process variations has a substantial impact on the power, performance, and reliability of products. These process variations can be local or across the chip or wafer-to-wafer, or even lot-to-lot. These process variations need to be observed and analyzed in order to improvise current design margins and also to understand the effect on product yield.
Silicon manufacturers usually put certain test structures in scribe line on selected wafers in each lot to observe and track the effects of process variation and DC characteristics of MOS devices, but these structures do not capture all the variation data. They also don’t provide explicit information to the designer about the corner the chip is running. Test structures like ring oscillators are generally used to get more information on a chip’s process corner. Such structures are placed at various locations across the chip to judge the effect of process variations on standard cell delays and performance.
Ring oscillator delays are an excellent indication of digital CMOS circuit performance. Variation in propagation delay can be measured through a ring oscillator implemented using finite stages of inverters, so the test structures (generally called as process monitors) comprising ring oscillators and digital frequency counters can be used for process performance and variation measurements. Usage of frequency dividers with multiplexers or JTAG TAP controllers gives more flexibility to observe low-frequency signals on CRO devices, too. All the access to and from the process monitor circuits can be done using the IEEE standard 1149 JTAG interface, and then it does not require any additional I/O ports.
While implementing an on-chip ring oscillator, care must be taken while selecting standard cells. This is necessary because the gate configuration is related to the variation in threshold voltage (VT), mobility, junction depth, etc. There are two ways to implement such structures:
1. Ring oscillators configured for the scenario where cell-delays are dominant.
2. Ring oscillators configured for the scenario where net delays are dominant.
In the first configuration, a fan-out of four (FO4) concept can be used for purely gate capacitance loading and avoiding long routing nets or parasitic loads. A similar approach can be used to understand parasitic delay variations by replacing digital gate capacitance loading with longer nets.
Because these test structures are included to monitor on-chip behavior of a given process node, it is a good idea to architect a ring oscillator for each device type (different VTs or channel length) used in the design, with inverter stages equivalent to average combinatorial logic depth, in order to have valuable data from these sensors. This provides the flexibility to figure out if the delay of any of these cell types differs from the library numbers under different PVT conditions.
Usefulness of the process monitor data
The ring oscillator data across the wafer is useful for process monitoring and for obtaining location based on-chip variation information.
1. Process monitoring. Observing ring oscillator frequency, the designer can determine if transistors are behaving differently than the pre-silicon measurements and can report the unusual variations to the foundry. The digital count of the ring oscillator frequency also helps to determine the silicon speed of the device. This information can be used to debug project yield as well as critical timing analysis problems.
2. Location-based OCV. Designers can use information from these on-chip process monitors to obtain a function of delay variation vs location. This information can be used to feedback location based OCV numbers for future design.
3. Enabling DVFS. In addition to process monitoring, the data from these test structures can be used to get maximum operating frequency vs die current relationship, to dynamically scale voltage and/or frequency (DVFS) according to the observed frequency of ring oscillator, etc.
Advantages of custom designed process monitors over off-the-shelf process monitor IPs
A custom-made process monitor can be fine-tuned for the design. For example, the number of inverter stages in a ring oscillator for a CPU should be much lower than that in a GPU as they have very different datapath logic depths.
Finally, custom process monitors allow us the flexibility to include/exclude a particular type of cell. For example, in a design without HVT cells, including a HVT ring oscillator occupies additional area and without providing any useful data. If one uses an off-the-shelf process monitor IP, this flexibility might not be always available.