A deeper understanding of chip design phases can significantly reduce costs.
Chip design is getting more and more challenging in terms of power, performance, area and IP integration. At the same time, competition and time-to-market are forcing much tighter schedules. The traditional ASIC design approach taken by OEMs is to handle the majority of front-end design in-house, and then hand off either register-transfer level (RTL) code or a netlist to an outside vendor, who will then handle physical design and manufacturing. However, because so much of what happens during front-end design can impact the overall success of a chip’s design, it’s important for companies to take a more holistic approach that considers back-end challenges from the start. With a holistic approach and a deeper understanding of the factors that should be taken into consideration at each design phase — from requirement and specification through to silicon — designers can accelerate design schedules while maintaining design integrity.
Requirement and specification
When specifying a chip, it’s important to define data points such as target market, desired performance, power targets, interface IP requirements and use cases. This input provides the foundation for a chip’s specification and architecture development. Power requirements should be very detailed, identifying power domains; dynamic voltage and frequency scaling; adaptive voltage and frequency scaling; and power modes. In addition, designers should specify die size, pin-count, IP configuration freeze and any custom IP requirements. It’s surprising how many designers continue to rely on static spreadsheets to analyze their architecture and performance, but many design pitfalls can be avoided by employing dynamic architecture analysis platforms and tools during this phase. Without them, designers risk either over- or under-designing a chip.
After defining the specification, front-end engineering can begin. Determining the different IP blocks, integrating these blocks and verifying the entire design is what this phase is all about. Companies must determine whether or not to source IP from a third-party or to develop it in-house, a decision that should be made after considering target application as well as the cost and maturity of the IP. In-house IP development often includes standard system blocks (power, clock, reset, debug, system registers, etc.) as well as custom IP blocks. Most companies have methodologies and tools such as auto code generation, and power and performance methodologies, that make it easier to develop these blocks.
Once sourced or developed, the IP must be integrated with the interconnect fabric to form a complete SoC. This requires a deep understanding of interconnect fabric selection, usage and optimization. Moreover, integration doesn’t end here. IP availability and maturity, as well as the desire for interconnect optimization, require constant adjustments throughout design. As a result, it becomes very important to have auto integration tools and methodologies.
Verification is a critical part of front-end design, and is often the most time-consuming. At this phase, designers should consider expanding their use of simulation to include use cases, boot code and power. These steps should be conducted using a proven methodology, and should be augmented with emulation and prototyping (virtual and FPGA) platforms to accelerate verification.
Physical design, manufacturing, package and test
As one of the lengthiest processes, physical design requires a lot of experience and resources. Physical design begins with analysis of the various metrics specified such as die size estimations, power requirements and package design options. Once complete, designers can begin exploring and implementing floor planning, IP hardening RTL partitioning, synthesis and static timing analysis and clock tree synthesis (CTS). In addition, they can optimize routing, CTS and timing violation. Formal, physical and noise verification should also be conducted during physical design, and different methodologies should be applied to address things like power, process variation, core performance, and test-time reduction. With respect to manufacturing, designers should consider the impact of different process options including pricing, flexibility and potential re-spin cost. Package and test options come with their own set of complexities like package design and simulation, prototype build support, manufacturing support, customer support, tester hardware design, electrical testing and silicon debug.
While most companies would be tempted to jump into software bring-up immediately after test, functional characterization should be run if the IP is not mature. Functional characterization covers block-level and system-level test at different corners and temperatures. Many times, issues that could cause a chip re-spin can be identified at this stage. Finally, designers should consider developing validation boards and pre-silicon validation test benches that can be enhanced and used for post-silicon validation, potentially saving significant time.
With a deeper understanding of the chip design phases, and a holistic approach to design, companies can significantly reduce the cost, time-to-market and risk that continues to grow with the complexity of each new process node.